This invention relates to specialized processing block for a programmable integrated circuit device such as, e.g., a programmable logic device (PLD), which can be configured for different levels of arithmetic precision.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® family, include DSP blocks, each of which may include four 18-by-18 multipliers. Each of those DSP blocks also may include adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed.
Such processing blocks have heretofore supported single-precision floating-point arithmetic operations (e.g., according to the IEEE754-1985 standard for floating-point arithmetic operations). Users who required higher levels of precision (the IEEE754-1985 standard provides for double-precision and quadruple-precision operations) have been required to configure higher-precision operations using general-purpose programmable resources of the programmable devices, possibly in conjunction with the single-precision processing blocks.